The invention relates to a process for fabricating an interconnect for contact holes and, in particular, to a process for the simple and inexpensive fabrication of an interconnect with contact holes that are free of disruptive voids.
The increasing complexity of integrated circuits and the rising packing density is, on one hand, increasing the number of interconnect or metallization layers of an integrated circuit while, on the other hand, a pattern size of contact holes for providing contact between the interconnect levels is decreasing. The contact holes serve to provide an electrical connection between the different interconnect levels or a substrate level on which electric circuits are formed. Filling up these contact holes or vias without producing voids and the simple patterning of the following interconnect level represents a key problem in the fabrication of an interconnect of an integrated circuit or a chip.
For example, the deposition of metal of upper metallization levels (second, third levels, etc.) often causes material to accumulate at the top edges of the contact hole or via, and such accumulation may even lead to deposition in the lower region of the contact hole becoming blocked and, therefore, to form what are referred to as voids. The problem increases with the progressively greater packing density or reduction in diameters for the contact holes and the tendency towards increasingly steep side walls of the contact holes in future size reduction processes, referred to as shrinks.
To fabricate such finely patterned contact holes with high aspect ratios in multiple interconnect levels, it has been customary to employ the four fabrication processes described below.
In what is referred to as a W-CVD process, tungsten is formed in the contact holes using a chemical vapor deposition (CVD) process, the process being distinguished by a good filling performance even with very small dimensions. However, such type of tungsten contact holes entail a large number of drawbacks that militate against using the process for the simple and inexpensive fabrication of an interconnect for contact holes. On one hand, there is a risk of an etching attack on a semiconductor substrate used from the WF6 used during the fabrication. Furthermore, tungsten exhibits poor adhesion to SiO2 and, consequently, causes possible contact problems. In particular, however, the heterogeneity of materials between tungsten contact holes and the respective metallization layers of the various interconnect levels, which preferably are made of Al alloys, cause differences in material flow. The differences in material flow lead to the preferential formation of voids at the interface between the tungsten contact holes and the metallization due to electromigration and stress migration. As such, the service life of the entire chip is impaired. Furthermore, the relatively high contact resistance compared to that of metallization levels or interconnect levels militates against the use of tungsten vias especially in future shrinks.
As an alternative to the tungsten deposition described above, it is possible to use chemical vapor deposition of an aluminum metallization (Al-CVD). However, the low deposition rates have meant that Al-CVD processes have been unable to gain acceptance for the mass production of integrated semiconductor circuits or chips. Furthermore, the high temperatures of xe2x89xa7500 degrees Celsius during the deposition lead to very large grains and associated difficulties in the subsequent patterning. Also, the Al-CVD process cannot be used to produce an alloy, such as, for example, Al-0.5% Cu, of the required quality. Therefore, such a process cannot be used for the simple and inexpensive fabrication of an interconnect.
A further possibility for the fabrication of contact holes or vias without voids is offered by what is referred to as the Al-PVD (physical vapor deposition) sputtering process at high temperatures of xe2x89xa7500 degrees Celsius. One modification to the physical vapor deposition process is in an initial cold deposition for the nucleation of Al nuclei and a subsequent increase in temperature during the sputtering. Although it is possible to achieve a good filling performance, with an improved reliability compared to that achieved using tungsten contact holes, the high temperatures during deposition of xe2x89xa7500 degrees Celsius means that the metallization layers or interconnect levels below are damaged by thermo-mechanical stress. Furthermore, very thick adhesion layers of Ti are required for filling gaps and voids by Al diffusion. This, together with the high temperature balance, leads to the formation of a pronounced TiAl3 layer, thus negating the advantage of the lower resistance compared to the tungsten contact holes.
A further possibility for the fabrication of an interconnect for contact holes is what are referred to as reflow processes. In such processes, the conventional sputtering is followed by a heat treatment at an elevated temperature of preferably xe2x89xa7500 degrees Celsius, during which a filler material is able to flow (reflow) into contact holes or their voids that have not previously been filled. Due to its low cost and simplicity, the process is particularly effective for mass production. However, the process, like the process described above, has the drawback of the damage caused to the metallization layers or interconnect levels below as a result of the high process or reflow temperature and the additional formation of a TiAl3 layer prior to patterning, with its unnecessarily high resistance. An alternative is offered by what are referred to as laser reflow processes, in which the subsequent heat treatment of the metallization or interconnect levels is controlled locally using a laser beam. Although this reduces the damage caused to lower metal levels, it does not allow inexpensive mass production.
Furthermore, for example, U.S. Pat. No. 5,789,317 to Batra et al. discloses a process in which, a sputtering deposition process is used to deposit AlGeCu in the contact holes using hydrogen (H) to fabricate an interconnect for contact holes. As such, it is possible to significantly reduce the flow properties and the risk of void formation. The use of hydrogen loosens the metal bonds and results in improved flow properties. However, because of the greatly increased roughness of the metal layer in the process, chemical mechanical polishing (CMP) has to be carried out first in a subsequent step, and a following interconnect layer that can be patterned easily and finely has to be applied to the entire area. However, these additional steps entail additional outlay, not least in terms of cost and time, with the further risk of deterioration in the contact.
It is accordingly an object of the invention to provide an interconnect for contact holes with small dimensions that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that simply and inexpensively allows reliable contact to be formed between different interconnect levels.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a process for fabricating an interconnect for contact holes, including the steps of: (a) forming contact holes in an insulation layer leading to a first interconnect layer, the insulation layer having an insulation surface, the contact holes having a hole surface; (b) cleaning the hole surface; (c) forming a barrier layer at least on the hole surface; (d) forming an AlGeCu-containing second interconnect layer on the insulation surface by a low-temperature PVD process to fill up the contact holes; (e) forming and patterning a mask layer; and (f) patterning the second interconnect layer by an anisotropic etching process using the mask layer.
In particular, the formation of an AlGeCu-containing second interconnect layer in order to fill the contact holes by a PVD process and the direct patterning of the second interconnect layer by an anisotropic etching process makes it possible to form contact holes without voids at low temperatures, so that there is no damage to lower interconnect levels or metallization layers. The formation of the intermetallic phase TiAl3, with the associated patterning difficulties, is minimized as a result. The AlGeCu layer that is formed has sufficiently small grain sizes to enable direct patterning by an anisotropic etching process. Consequently, the CMP (chemical mechanical polishing) step that is usually present can be eliminated, thus, further simplifying the process.
In accordance with another mode of the invention, preferably, the second interconnect layer is formed in a single-stage process by deposition of an AlGeCu layer at substrate temperatures of  greater than 100 degrees Celsius. Usually, however, the substrate temperatures are below 420 degrees Celsius and, therefore, well below what is referred to as the reflow temperature of  greater than 500 degrees Celsius. As such, the second interconnect layer can be deposited relatively quickly in the contact holes without the formation of voids.
In accordance with a further mode of the invention, the second interconnect layer can be deposited in a two-stage process by deposition of a first AlGeCu layer at low temperatures and of a second AlGeCu layer at high substrate temperatures. Such formation results in the further improvement of the filling properties in the contact holes. Preferably, the second interconnect layer is formed in a two-stage process by depositing a first AlGeCu layer at a substrate temperature of  less than 100 degrees Celsius and depositing a second AlGeCu layer at a substrate temperature of  greater than 100 degrees Celsius.
In accordance with an added mode of the invention, in a two-stage process the second interconnect layer can also be formed by depositing an AlCu layer at low substrate temperatures of  less than 100 degrees Celsius and an AlGeCu layer at higher substrate temperatures of  greater than 100 degrees Celsius. The result of such a process is improved filling properties and contact resistances combined with shortened deposition times.
In accordance with an additional mode of the invention, the second interconnect layer can be formed in a three-stage process by depositing a first AlCu layer, an AlGeCu layer, and a second AlCu layer. As a result, improved contact resistances and optimum patterning properties are achieved while maintaining optimum flow properties.
In accordance with yet another mode of the invention, the second interconnect layer forming step includes subjecting the second interconnect layer including at least one of the contact holes to a final heat treatment.
In accordance with yet a further mode of the invention, the second interconnect layer is formed in a multi-stage process by depositing at least one AlGeCu layer in the contact holes, followed by planarizing by chemical mechanical polishing, and by depositing an AlCu layer over an entire area of the insulation surface.
In accordance with yet an added mode of the invention, the cleaning step is performed by wet-chemical cleaning and/or a plasma-etching process.
In accordance with yet an additional mode of the invention, the barrier layer used is preferably a Ti adhesion layer having a thickness that can be reduced further, due to the improved flow properties, therefore, allowing even smaller pattern sizes.
In accordance with again another mode of the invention, before the mask layer forming and patterning step, an antireflection layer is formed on the surface of the second interconnect layer.
In accordance with again a further mode of the invention, a TiN layer is formed as the antireflection layer.
In accordance with again an added mode of the invention, a Ge-containing AlCu target is used to form the second interconnect layer.
In accordance with a concomitant mode of the invention, the patterning step is performed by reactive ion etching. Reactive ion etching directly on the second interconnect layer is preferably employed for the anisotropic etching process, so that the process is particularly easy to integrate into existing fabrication processes.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a process for the fabrication of an interconnect for contact holes with small dimensions, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.